EDA知识，求VHDL语言描述急求答案

EDA知识，求VHDL语言描述急求答案

将下面两个vhd文件放到同一个工程项目中编译即可：
library ieee;
use ieee.std_logic_1164.all;
entity div_5_6 is
port (dk:in std_logic;
dk5,dk6:out std_logic);
end div_5_6;
architecture structural of div_5_6 is
component div_n is
generic(n:integer :=6);
port (clk:in std_logic;
q:out std_logic);
end component;
begin
U5:div_n generic map(n => 5)
port map(clk => dk, q => dk5);
U6:div_n generic map(n => 6)
port map(clk => dk, q => dk6);
end structural;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_n is
generic(n:integer :=6);
port (clk:in std_logic;
q:out std_logic);
end div_n;
architecture behavioral of div_n is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if rising_edge(clk) then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behavioral;