用VHDL语言编写十进制计数译码显示电路，在一个程序中用块形式编写，高手给答案不

用VHDL语言编写十进制计数译码显示电路，在一个程序中用块形式编写，高手给答案不

process(data_in,add_pul,reg_count)--在输入数据的基础上加1
begin
if falling_edge(add_pul) then--下降沿加数
if data_in(3 downto 0) >= "1001" then
reg_count(3 downto 0) <= "0000";
if data_in(7 downto 4) >= "1001" then
reg_count(7 downto 4) <= "0000";
else
reg_count(7 downto 4) <= data_in(7 downto 4)+1;
end if;
else
reg_count(3 downto 0) <= data_in(3 downto 0)+1;
reg_count(7 downto 4) <= data_in(7 downto 4);
end if;
end if;
if rising_edge(add_pul) then--上升沿赋值
addbcd <= reg_count;
end if;
end process;

library ieee; use ieee.std_logic_1164.all; entity smg_16 is port( a:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0) ); end smg_16; architecture bhv of smg_16 is begin process(a) begin case a is when "0000"=> q<="0