如何定义 coverpoint system verilog

module flowadd(ix, iy, ze, zm, clk, a_en, ost);    input ix, iy, clk, a_en;    output ze, zm, ost;       wire[31:0]   ix, iy;    wire   clk, ost;         //reg[31:0] z, x, y;    reg[24:0]    xm, ym, zm;      //the [ c 1. m ]   incldue 1-bit reg "c" for upflow but not sign     //   and include 3-bit reg for downward overflow     //   so the fragment point is before the 3th    reg[7:0]    xe, ye, ze;   //exponent    reg mc, ms;    reg[2:0] state;       parameter   start =   3'b000,     zerock =  3'b001,     exequal = 3'b010,     addm =    3'b011,     infifl =  3'b100,     zerofl =  3'b101,     over =    3'b110,     idle =    3'b