高手进 急求一段十五进制同步计数器VHDL语言程序

高手进 急求一段十五进制同步计数器VHDL语言程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tk4757_div1000 is
port(clk:in std_logic;
co:out std_logic);
end;
architecture behav of tk4757_div1000 is
signal bcd:integer range 14 downto 0;
begin
process(clk)
begin
if clk'event and clk='1' then
if bcd=14 then
bcd<=0;
co<='1';
else bcd<=bcd+1;
co<='0';
end if;
end if;
end process;
end behav;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity 8_count is port(clk,reset,en:in std_logic; output:out integer range 0 to 7); end entity; architecture art of 8_count is begin process(clk,reset,en) variable cnt:integer range 0 to 7 begin if reset='1' then cnt:=0; elsif clk'event and clk='1' then if en='1' then cnt:=cnt+1; else cnt:=0; end if; end if; output&lt;=cnt; end process; end art;