急求一份基于FPGA的电子钟（时分秒显示、校时、定时闹钟等功能） 源代码

急求一份基于FPGA的电子钟（时分秒显示、校时、定时闹钟等功能） 源代码

写了段代码，供参考。

module clock(clk,rst,set, set_typ, set_data, yr, mon, dt, hr, min, sec,
alarm_en, alm_typ, alm_yr, alm_mon, alm_dt, alm_hr, alm_min, alm_sec, alarm_output);
input clk,rst,set;
input [2:0] set_typ; //
input [6:0] set_data;//
output [6:0] yr, mon, dt, hr, min, sec;

input alarm_en;
input [2:0] alm_typ; //
input [6:0] alm_yr, alm_mon, alm_dt, alm_hr, alm_min, alm_sec;
output alarm_output;

parameter C_FR = 32'd20_000_000-32'd1; //定义系统时钟20MHz

reg [31:0] fr_cnt;
reg [3:0] sec_cnt;

reg pp1s; //秒脉冲
//==================================================
//fr_cnt
always@(posedge clk)//
if(!rst)
fr_cnt <= 32'b0;
else if (fr_cnt >= C_FR)
fr_cnt <= 32'b0;
else
fr_cnt <= fr_cnt + 1'b1;

//pp1s
always@(posedge clk)//
if(!rst)
pp1s <= 1'b0;
else if (fr_cnt == C_FR)
pp1s <= 1'b1;
else
pp1s <= 1'b0;

///time counter
always@(posedge clk)
if(!rst)
begin
yr <= 7'b0;
mon <= 7'b0;
dt <= 7'b0;
hr <= 7'b0;
min <= 7'b0;
sec <= 7'b0;
end
else if (set)
begin
case (set_typ)
3'b000: yr <= set_data;
3'b001: mon <= set_data;
3'b010: dt <= set_data;
3'b011: hr <= set_data;
3'b100: min <= set_data;
3'b101: sec <= set_data;
end
else if (pp1s)
begin
if (sec >= 7'd59)
sec <= 7'd0;
else
sec <= sec + 1'b1;

if (sec >= 7'd59)
begin
if (min >= 7'd59)
min <= 7'd0;
else
min <= min + 1'b1;
end

if (sec >= 7'd59 && min >= 7'd59)
begin
if (hr >= 7'd23)
hr <= 7'd0;
else
hr <= hr + 1'b1;
end

///data,mon, year, 大月小月，闰年等，依此类推
//
end

//=================================
//alarm
always@(posedge clk)
if(!rst)
alarm_output <= 1'b0;
else if (alarm_en)
case (alm_typ)
3'b000:
if (yr == alm_yr && mon == alm_mon && dt == alm_dt && hr == alm_hr && min == alm_min && sec == alm_sec)
alarm_output <= 1'b1;
else
alarm_output <= 1'b0;
3'b001:
if (mon == alm_mon && dt == alm_dt && hr == alm_hr && min == alm_min && sec == alm_sec)
alarm_output <= 1'b1;
else
alarm_output <= 1'b0;
3'b010:
if (dt == alm_dt && hr == alm_hr && min == alm_min && sec == alm_sec)
alarm_output <= 1'b1;
else
alarm_output <= 1'b0;
3'b011:
if (hr == alm_hr && min == alm_min && sec == alm_sec)
alarm_output <= 1'b1;
else
alarm_output <= 1'b0;
3'b100:
if (min == alm_min && sec == alm_sec)
alarm_output <= 1'b1;
else
alarm_output <= 1'b0;
default
alarm_output <= 1'b0;
endcase

endmodule

verilog语言可以嘛？
VHDL语言，写起来有点麻烦……