你好，我想用VHDL检测两个外部信号的上升沿之间的时间差，应该怎么写代码啊？

你好，我想用VHDL检测两个外部信号的上升沿之间的时间差，应该怎么写代码啊？

我做了两个输入信号（Signal_1，Signal_2）的上升沿检测（Edge_1，Edge_2），然后以Edge_1开始count，Edge_2终了count。
这样时间差就是count的值，输出是CntOut。时间差和你的时钟也有关。

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--shift input to detect edge
process(CLK, nRESET)
begin
if nRESET = '0' then
Signal_1 <= '0';
Signal_2 <= '0';
elsif CLK'event and CLK = '1' then
rSignal_1 <= Signal_1;
rSignal_2 <= Signal_2;
end if;
end process;

--here is posedge
Edge_1 <= Signal_1 and (not rSignal_1);
Edge_2 <= Signal_2 and (not rSignal_2);
--posedge state from signal_1 to signal_2
process(CLK, nRESET)
begin
if nRESET = '0' then
StateOn <= '0';
elsif CLK'event and CLK = '1' then
if (Edge_1 == '1') then
StateOn <= '1';
elsif (Edge_2 == '1') then
StateOn <= '0';
end if;
end if;
end process;

--interval between edge
process(CLK, nRESET)
begin
if nRESET = '0' then
Cnt <= (others=>'0');
elsif CLK'event and CLK = '1' then
if (StateOn == '1') then
Cnt <= Cnt + '1';
else
Cnt <= (others=>'0');
end if;
end if;
end process;

--output interval
process(CLK, nRESET)
begin
if nRESET = '0' then
CntOut <= (others=>'0');
elsif CLK'event and CLK = '1' then
if (Edge_2 == '1') then
CntOut <= Cnt;
end if;
end if;
end process;追问非常感谢，晚上验证一下，谢谢！追答用时钟打一拍 然后逻辑电路一下就可以了