求基于VHDL的4位数字密码锁的论文

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY D_RF IS
PORT(D : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC);
END D_RF;

ARCHITECTURE ONE OF D_RF IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='0' THEN
Q1<=D;Q2<= NOT D;
END IF;
END PROCESS;
END ONE;

这是下降沿触发的。