VHDL编写ROM的程序能把你的给我看看吗谢谢

VHDL编写ROM的程序能把你的给我看看吗谢谢

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY mc8051_rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END mc8051_rom;

ARCHITECTURE SYN OF mc8051_rom IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);

COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN
q <= sub_wire0(7 DOWNTO 0);

altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
init_file => "p1test.hex",
intended_device_family => "Cyclone",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M4K",
widthad_a => 12,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);

END SYN;