Error (10482): VHDL error at yimaqi.vhdl(12): object "q" is used but not declared为什么一共四处错

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY yimaqi IS
PORT(q_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
led:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE bhv OF yimaqi IS
BEGIN
PROCESS(q)
BEGIN
CASE q IS
WHEN "0000" => led <="11111100";
WHEN "0001" => led <="01100000";
WHEN "0010" => led <="11011010";
WHEN "0011" => led <="11110010";
WHEN "0100" => led <="01100110";
WHEN "0101" => led <="10110110";
WHEN "0110" => led <="10111100";
WHEN "0111" => led <="11100000";
WHEN "1000" => led <="11111110";
WHEN "1001" => led <="11110110";
WHEN "1010" => led <="11101110";
WHEN "1011" => led <="00111110";
WHEN "1100" => led <="10011110";
WHEN "1101" => led <="01111010";
WHEN "1110" => led <="10011110";
WHEN "1111" => led <="10001110";
WHEN OTHERS => led <="11111111";
END CASE;
END PROCESS;
END;

你在进程中出现的信号q没有被声明过，应当用端口声明中的q_in。
至于出错提示中的错误个数，并非指描述中出现的次数。通常你将最前面出现的错误改正之后，其余错误提示也就随之消失了。

期待看到有用的回答！