Error (10170): Verilog HDL syntax error at yiwei.v(11) near text "else"; expecting ";

module yiwei(in,sr,lr,clk,out);
input[7:0] in ;input clk sr,lr;
output reg[7:0] out;
integer i;
always @ (posedge clk)

begin if(~lr)
out[0]=sr;
for(i=1;i<=7;i=i+1)
out[i]=in[i-1];
else
out[7]=sr;
for(i=0;i<=6;i=i+1)
out[i]=in[i+1];

end
endmodule
出现错误不知道为什么？

if后面携带的赋值语句如果多于1个，则用begin end 括起来。else也同样。