12归1程序如下：LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY twelveto1 IS
PORT(finclk：IN STD_LOGIC;
outputa：OUT STD_LOGIC_VECTOR(6DOWNTO 0);
outputb：OUT STD_LOGIC_VECTOR(6DOWNTO 0));
END twelveto1；
ARCHTECTURE arch_twelveto1 of twelveto1 IS
SIGNAL sa:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sb:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL f:STD_LOGIC;
COMPONENT fp
PORT(inclk:IN STD_LOGIC;
outputf:OUT STD_LOGIC);
END COMPONENT;
BEGIN
u1:fp
PORT MAP(inclk=>finclk,outputf=>f);
PROCESS(f)
BEGIN
IF(rising_edge(f)) THEN
IF (sa=2and sb=1)THEN
sa<="0001"
sb<="0000";
ELSE
IF sa=9 THEN
sa<="0000";
sb<=sb+1;
ELSE
sa<=sa+1;
END IF;
END IF;
END PROCESS;
WITH sa SELECT
outputa<="0110000" when "0001",
"1101101" when "0010",
"1111001"when "0011",
"0110011" when "0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0011111"when"1011"
"1001110"when"1100",
"0111101"when"1101:,
"1001111"when"1110",
"1000111"when"1111",
"1111110"when others;
with sb select
outputb<="0110000" when "0001",
"1101101" when "0010",
"1111001"when "0011",
"0110011" when "0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0011111"when"1011"
"1001110"when"1100",
"0111101"when"1101:,
"1001111"when"1110",
"1000111"when"1111",
"1111110"when others;
END arch_twelveto1;