用VHDL语言设计一个二输入五输出(与门、或门、与非门、或非门、异或门)的逻辑器

用VHDL语言设计一个二输入五输出(与门、或门、与非门、或非门、异或门)的逻辑器

道Library ieee;
Use ieee.std_logic_1164.all;
Entity gate is
Port(a,b:in std_logic;
c_and:out std_logic;
d_or:out std_logic;
e_nand:out std_logic;
f_nor:out std_logic;
g_xor:out std_logic
);
End gate;
Architecture behave of gate is
Begin
c_and<=a and b;
d_or<=a or b;
e_nand<=a nand b;
f_nor<=a nor b;
g_xor<=((not a)and b)or(a and (not b));
End behave;