根据黄继业编写的EDA技术与VHDL的第六章做的CPU出现的问题，纠结了一天了，具体的看问题补充，拜托了

这是自定义的库
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package cpu_lib is
type t_shift is (shftpass, shl, shr, rotl, rotr,sel); --
subtype t_alu is unsigned(3 downto 0); --
constant alupass: unsigned (3 downto 0) := "0000"; -- 通过
constant andOp: unsigned(3 downto 0) := "0001"; -- 与运算
constant orOp: unsigned(3 downto 0) := "0010"; -- 或运算
constant notOp: unsigned(3 downto 0) := "0011"; -- 非运算
constant xorOp: unsigned(3 downto 0) := "0100"; -- 异或运算
constant plus: unsigned(3 downto 0) := "0101"; -- 加法
constant alusub: unsigned(3 downto 0) := "0110"; -- 减法
constant inc: unsigned(3 downto 0) := "0111"; -- 加1
constant dec: unsigned(3 downto 0) := "1000"; -- 减1
constant zero: unsigned(3 downto 0) := "1001"; -- 清零
type t_comp is (eq, neq, gt, gte,lt, lte);

subtype t_reg is std_logic_vector(2 downto 0); --
end cpu_lib;
这是COMP文件的一部分
use work.CPU_LIB.all;
entity COMP is
port ( A, B : in bit16; sel: in t_comp; COMPOUT : out std_logic);
end COMP;
问题出现在这里了：Error (10017): Can't create symbol/include/instantiation/component file for entity "COMP" because port "sel" has an unsupported type

同样的control文件也出现这个问题
library IEEE;
use IEEE.std_logic_1164.all;
USE work.cpu_lib.ALL;
entity control is --
port (clock, reset, ready : in std_logic; -- 时钟，复位，数据ready
instrReg : in bit16; -- 指令译码输入
instrWr : out std_logic; -- 指令寄存器写入控制
compout : std_logic; -- 比较结果输入 compSel : out t_comp; -- 比较方式选择
aluSel : out t_alu; -- 运算方式选择
shiftSel : t_shift; -- 移位方式选择
regSel : out t_reg; -- 寄存器阵列选择 regWr,regRd : out std_logic; -- 寄存器阵列写入/读出控制
opRegWr,opRegRd : out std_logic; -- 工作寄存器写入/读出控制
outRegWr,outRegRd : out std_logic; -- 输出寄存器写入/读出控制
progCntrWr,progCntrRd : out std_logic; -- PC寄存器写入/读出控制
addrRegWr,addrRegRd : out std_logic; -- 地址寄存器写入/读出控制
rw,vma : out std_logic); -- 存储器读写、片选控制
end control;
问题
Error (10017): Can't create symbol/include/instantiation/component file for entity "control" because port "compSel" has an unsupported type
Error (10017): Can't create symbol/include/instantiation/component file for entity "control" because port "shiftSel" has an unsupported type

port ( A, B : in bit16; sel: in t_comp; COMPOUT : out std_logic);
t_comp这个数据类型不存在啦