求8*8位流水线乘法器的Quartus的原理图或者VHDL代码！急用，谢谢！

求8*8位流水线乘法器的Quartus的原理图或者VHDL代码！急用，谢谢！

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Test is
port(
clk :in std_logic;
a :in std_logic_VECTOR(7 downto 0);
b :in std_logic_VECTOR(7 downto 0);
cout:out std_logic_VECTOR(15 downto 0)
);
end Test;

architecture Test of Test is
signal a1,b1:std_logic_vector(3 downto 0);
signal a2,b2:std_logic_vector(7 downto 4);
signal cout1:std_logic_vector(15 downto 0);
signal cout2:std_logic_vector(15 downto 0);
signal a1b1,a2b1,a1b2,a2b2:std_logic_vector(15 downto 0);
begin
process(a,b,clk)
begin
if clk'event and clk='1' then
a1b1<="0000"&(a(5 downto 0) *b(5 downto 0));
a2b1<="00"&(a(7 downto 6)*b(5 downto 0))&"000000";
a1b2<="00"&(a(5 downto 0)*b(7 downto 6))&"000000";
a2b2<=(a(7 downto 6)*b(7 downto 6))&"000000000000";
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
cout1<=a1b1+a2b1;
cout2<=a1b2+a2b2;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
cout<=cout1+cout2;
end if;
end process;
end Test;

这个可以用~试试吧！

你没楼上的在搞笑？看哥哥给你3分钟搞一个！

http://202.115.21.138/wlxt/ncourse/xddzsy/web/jp/wlxt/syzd4/stage4-1.htm去这看看 应该有你想要的

--h_suber
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_suber IS
PORT(x,y: IN STD_LOGIC;
diff,s_out:OUT STD_LOGIC);
END h_suber;
ARCHITECTURE behav OF h_suber IS
BEGIN
diff<=x XOR y;
s_out<=(NOT x) AND y;
END behav;
--end h_suber
--f_suber
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_suber is
PORT(fx,fy,sub_in:IN STD_LOGIC;
diffr,sub_out:OUT STD_LOGIC);
END ENTITY f_suber;
ARCHITECTURE behav OF f_suber IS
COMPONENT h_suber
PORT(x,y : IN STD_LOGIC;
diff,s_out:OUT STD_LOGIC);
END COMPONENT;
SIGNAL a,b,c : STD_LOGIC;
BEGIN
u1:h_suber PORT MAP(x=>fx,y=>fy,diff=>a,s_out=>b);
u2:h_suber PORT MAP(x=>a,y=>sub_in,diff=>diffr,s_out=>c);
sub_out<=b AND c;
END behav;
--end f_suber
--f_suber8
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_suber8 IS
PORT(fx8,fy8 :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sub_in8: IN STD_LOGIC;
diff8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out8: OUT STD_LOGIC);
END ENTITY f_suber8;
ARCHITECTURE behav OF f_suber8 IS
COMPONENT f_suber
PORT(fx,fy,sub_in:IN STD_LOGIC;
diffr,sub_out:OUT STD_LOGIC);
END COMPONENT;
SIGNAL s_outs: STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
u1 : f_suber PORT MAP(fx=>fx8(0),fy=>fy8(0),sub_in=>sub_in8,diffr=>diff8(0),sub_out=>s_outs(0));
u2 : f_suber PORT MAP(fx=>fx8(1),fy=>fy8(1),sub_in=>s_outs(0),diffr=>diff8(1),sub_out=>s_outs(1));
u3 : f_suber PORT MAP(fx=>fx8(2),fy=>fy8(2),sub_in=>s_outs(1),diffr=>diff8(2),sub_out=>s_outs(2));
u4 : f_suber PORT MAP(fx=>fx8(3),fy=>fy8(3),sub_in=>s_outs(2),diffr=>diff8(3),sub_out=>s_outs(3));
u5 : f_suber PORT MAP(fx=>fx8(4),fy=>fy8(4),sub_in=>s_outs(3),diffr=>diff8(4),sub_out=>s_outs(4));
u6 : f_suber PORT MAP(fx=>fx8(5),fy=>fy8(5),sub_in=>s_outs(4),diffr=>diff8(5),sub_out=>s_outs(5));
u7 : f_suber PORT MAP(fx=>fx8(6),fy=>fy8(6),sub_in=>s_outs(5),diffr=>diff8(6),sub_out=>s_outs(6));
u8 : f_suber PORT MAP(fx=>fx8(7),fy=>fy8(7),sub_in=>s_outs(6),diffr=>diff8(7),sub_out=>s_out8);
END behav;
--end f_suber8