求帮编一个verilog的tb测试程序
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解决时间 2021-04-07 12:05
- 提问者网友:浪荡绅士
- 2021-04-06 12:15
求帮编一个verilog的tb测试程序
最佳答案
- 五星知识达人网友:duile
- 2021-04-06 13:53
module t;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Co;
reg Sel;
// Outputs
wire [3:0] S;
wire C;
wire V;
// Instantiate the Unit Under Test (UUT)
adder_4 uut (
.A(A),
.B(B),
.S(S),
.Co(Co),
.C(C),
.V(V),
.Sel(Sel)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
Co = 0;
Sel = 0;
// Wait 100 ns for global reset to finish
#100;
A = 0;
B = 0;
Co = 0;
Sel = 1;
#100;
A = 4;
B = 5;
Co = 1;
Sel = 1;
#100;
A = 10;
B = 2;
Co = 0;
Sel = 1;
#100;
A = 10;
B = 2;
Co = 0;
Sel = 0;
// Add stimulus here
end
endmodule
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