能看懂芯片说明的大大，帮忙翻一下这几段英文。自动翻译就算了

Workaround 1: The DDR3 PHY in the device has the ability to complete auto-leveling of the write leveling values and the read DQS gate training values separate from the read data eye training. Then a single value is used as the read data eye sample point. This solution is functional on standard DDR3 fly-by layouts. It has been shown to operate robustly at DDR3-1333 when connected to a UDIMM but this rate may need to be derated for long-term operation.

This mode is enabled by setting bit 9 (0-indexed) of the DDR3_CONFIG_REG_23 at address 0x02620460. The lower 8 bits (bits 7:0) will be loaded with the read data eye sample point. At this time, we recommend programming this value to 0x50.
Auto-leveling is enabled after bit 9 of the register DDR3_CONFIG_REG_23 above is set.

Workaround 2: The user has the ability to completely disable the automatic leveling features of the DDR3 controller and rely exclusively on a set of ratio-forced register values. These values control the DQ and DQS delay between all byte lanes for gate leveling, write leveling, and read data eye training. The specific registers and values to set in the registers are described in the KeyStone Architecture DDR3 Memory Controller User Guide (literature number SPRUGV8). The values programmed are dependent on the specific board characteristics.

Because these delay values cannot be tailored to specific byte lanes, only layouts with very small signal skews between DRAMs can use this workaround. Rather that following the routing guidelines which allow different lengths for each byte lane, all signals must be closely matched. Specifically:
1. Route lengths for address, command, control and clock between the DSP and DRAMs must be very similar. We understand that the fly-by topology prevents these lengths from matc

看到workaround就忍不住要叹气了。这八成又是什么芯片的勘误手册吧。

只是告诉你手机的销售地和颜色 不一定要翻译完

销售地：荷兰    颜色：白色