Error (10327): VHDL error at seg.vhd(13): can't determine definition of operator ""&&q

Error (10327): VHDL error at seg.vhd(13): can't determine definition of operator ""&""

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seg is
port(b,a:in std_logic;
seg7:buffer std_logic_vector(6 downto 0);
dig1,dig2:out std_logic);
end seg;
architecture two of seg is
signal clk_a: std_logic_vector(1 downto 0);---------修改
begin
clk_a<=a&b;
process(clk_a)--------敏感向量修改
begin
case clk_a is
when "00"=>dig1<='1';dig2<='0';
when "01"=>dig1<='0';dig2<='1';
when others=>null;
end case;
end process;
end two;