要求:用正电频为驱动电频32秒后还原设计秒脉冲!只需要设计图~~
用vhdl编写5人电子抢答器
答案:1 悬赏:0 手机版
解决时间 2021-04-13 02:16
- 提问者网友:兔牙战士
- 2021-04-12 11:37
最佳答案
- 五星知识达人网友:走死在岁月里
- 2021-04-12 12:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.all;
use ieee.std_logic_UNSIGNED.all;
ENTITY BIAOJUE IS
PORT( FF:IN STD_LOGIC_VECTOR(1 TO 5);
QQ:OUT BIT;
QALL:OUT STD_LOGIC_VECTOR(3 DOWNTO 1);
SHIJIAN:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
FUWEI,KAISHI,CLK:IN STD_LOGIC);
END BIAOJUE;
ARCHITECTURE FUNG OF BIAOJUE IS
BEGIN
PROCESS(FF,CLK,KAISHI,FUWEI)
VARIABLE SUO:BOOLEAN;
VARIABLE SUM:STD_LOGIC_VECTOR(1 TO 3);
BEGIN
IF (FUWEI='0') THEN
QQ<='0';
SHIJIAN<="1010";
SUO:=FALSE;
SUM:="000";
QALL<="000";
ELSIF (CLK'EVENT AND CLK='1') THEN
IF (KAISHI='1') THEN
IF (NOT SUO) THEN
IF SHIJIAN="0000" THEN
SUO:=TRUE;
FOR N IN 1 TO 5 LOOP
SUM:=FF(N)+SUM;
END LOOP;
ELSE
SHIJIAN<=SHIJIAN-1;
END IF;
END IF;
QALL<=SUM;
IF (SUM >= 3) THEN
QQ<='1';
ELSE
QQ<='0';
END IF;
END IF;
END IF;
END PROCESS;
END FUNG;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.all;
use ieee.std_logic_UNSIGNED.all;
ENTITY BIAOJUE IS
PORT( FF:IN STD_LOGIC_VECTOR(1 TO 5);
QQ:OUT BIT;
QALL:OUT STD_LOGIC_VECTOR(3 DOWNTO 1);
SHIJIAN:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
FUWEI,KAISHI,CLK:IN STD_LOGIC);
END BIAOJUE;
ARCHITECTURE FUNG OF BIAOJUE IS
BEGIN
PROCESS(FF,CLK,KAISHI,FUWEI)
VARIABLE SUO:BOOLEAN;
VARIABLE SUM:STD_LOGIC_VECTOR(1 TO 3);
BEGIN
IF (FUWEI='0') THEN
QQ<='0';
SHIJIAN<="1010";
SUO:=FALSE;
SUM:="000";
QALL<="000";
ELSIF (CLK'EVENT AND CLK='1') THEN
IF (KAISHI='1') THEN
IF (NOT SUO) THEN
IF SHIJIAN="0000" THEN
SUO:=TRUE;
FOR N IN 1 TO 5 LOOP
SUM:=FF(N)+SUM;
END LOOP;
ELSE
SHIJIAN<=SHIJIAN-1;
END IF;
END IF;
QALL<=SUM;
IF (SUM >= 3) THEN
QQ<='1';
ELSE
QQ<='0';
END IF;
END IF;
END IF;
END PROCESS;
END FUNG;
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