4、试写出4选1多路选择器的VHDL描述，假设选择控制信号为S1、S0，输入信号为d3,d2,d1,d0，输出信号为y。
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解决时间 2021-01-10 14:27
- 提问者网友：不爱我么
- 2021-01-10 03:01
4、试写出4选1多路选择器的VHDL描述，假设选择控制信号为S1、S0，输入信号为d3,d2,d1,d0，输出信号为y。
最佳答案
- 五星知识达人网友：时间的尘埃
- 2021-01-10 03:19
ENTITY mux4 IS
PORT( d3,d2,d1,d0: IN bit;
s1,s0: IN bit;
y: OUT bit);
END mux4;
ARCHITECTURE one OF mux4 IS
BEGIN
PROCESS(d3,d2,d1,d0,s1,s0)
BEGIN
CASE s1&s0 IS
WHEN "11" => y <= d3;
WHEN "10" => y <= d2;
WHEN "01" => y <= d1;
WHEN "00" => y <= d0;
END CASE;
END PROCESS;
END one;
PORT( d3,d2,d1,d0: IN bit;
s1,s0: IN bit;
y: OUT bit);
END mux4;
ARCHITECTURE one OF mux4 IS
BEGIN
PROCESS(d3,d2,d1,d0,s1,s0)
BEGIN
CASE s1&s0 IS
WHEN "11" => y <= d3;
WHEN "10" => y <= d2;
WHEN "01" => y <= d1;
WHEN "00" => y <= d0;
END CASE;
END PROCESS;
END one;
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