LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_adder_8 IS
PORT(A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ci : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
co : OUT STD_LOGIC);
END ENTITY f_adder_8 ;
ARCHITECTURE fd OF f_adder_8 IS
COMPONENT f_adder
PORT(ain, bin, cin : IN STD_LOGIC;
cout, sum : OUT STD_LOGIC );
END COMPONENT ;
SIGNAL cout1, cout2, cout3, cout4, cout5, cout6, cout7 : STD_LOGIC;
BEGIN
u1 : f_adder PORT MAP(a(0)=>ain, b(0)=>bin, ci=>cin, cout=>cout1, sum=>s(0));
u2 : f_adder PORT MAP(a(1)=>ain, b(1)=>bin, cout1=>cin, cout=>cout2, sum=>s(1));
u3 : f_adder PORT MAP(a(2)=>ain, b(2)=>bin, cout2=>cin, cout=>cout3, sum=>s(2));
u4 : f_adder PORT MAP(a(3)=>ain, b(3)=>bin, cout3=>cin, cout=>cout4, sum=>s(3));
u5 : f_adder PORT MAP(a(4)=>ain, b(4)=>bin, cout4=>cin, cout=>cout5, sum=>s(4));
u6 : f_adder PORT MAP(a(5)=>ain, b(5)=>bin, cout5=>cin, cout=>cout6, sum=>s(5));
u7 : f_adder PORT MAP(a(6)=>ain, b(6)=>bin, cout6=>cin, cout=>cout7, sum=>s(6));
u8 : f_adder PORT MAP(a(7)=>ain, b(7)=>bin, cout7=>cin, cout=>co, sum=>s(7));
END ARCHITECTURE fd;
Error (10482): VHDL error at f_adder_8.vhd(16): object "ain" is used but not declared
Error (10482): VHDL error at f_adder_8.vhd(16): object "bin" is used but not declared
Error (10349): VHDL Association List error at f_adder_8.vhd(16): formal "ci" does not exist
Error (10346): VHDL error at f_adder_8.vhd(16): formal port or parameter "ain" must have actual or default value