EDA项目设计
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解决时间 2021-11-26 17:00
- 提问者网友：寂寞梧桐
- 2021-11-26 00:19
EDA项目设计
最佳答案
- 五星知识达人网友：风格不统一
- 2021-11-26 01:28
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY downcount is
port(clk:in std_logic;
reset:in std_logic;
q:out std_logic_vector(4 downto 0));
end entity;
architecture tr1 of downcount is
signal count:std_logic_vector(4 downto 0);
begin
process(clk,reset)
begin
if clk'event and clk='1' then
if reset='0' then
count<=(others=>'1');
else
count<=count-1;
end if;
end if;
end process;
q<=count;
end tr1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY downcount is
port(clk:in std_logic;
reset:in std_logic;
q:out std_logic_vector(4 downto 0));
end entity;
architecture tr1 of downcount is
signal count:std_logic_vector(4 downto 0);
begin
process(clk,reset)
begin
if clk'event and clk='1' then
if reset='0' then
count<=(others=>'1');
else
count<=count-1;
end if;
end if;
end process;
q<=count;
end tr1;
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