如何使UltraEdit支持Verilog语法高亮缩进

如何使UltraEdit支持Verilog语法高亮缩进

1.
将Verilog和VHDL语言高亮的代码分别保存为文件Verilog.uew和VHDL.uew，并将其放在ultraedit15.0安装目录中的wordfiles文件夹下；

wordfiles的默认路径是：

C:\Documents and Settings\（电脑用户名）\Application
Data\IDMComp\UltraEdit\wordfiles

Verilog.uew文件内容（文件自己创建即可）：

/L11"Verilog" V_LANG Line Comment = // Block Comment On = Escape
Char = \ String Chars = " File Extensions = V TF
/Delimiters = ~#!@%^&*()-+=|\/{}[]:;"<>
, .?
/Function String = "%[a-zA-Z_0-9]* ^([a-zA-Z_0-9]+^)[
^t]++(*)[~;]"
/Function String 1 = "%[a-zA-Z_0-9]*::^([a-zA-Z_0-9]+^)[
^t]++(*)[~;]"
/Indent Strings = "begin"
/Unindent Strings = "end"
/Open Brace Strings = "{" "(" "["
/Close Brace Strings = "}" ")" "]"
/Open Fold Strings = "begin" "case" "fork"
/Close Fold Strings = "end" "endcase" "join"
/C1"Keywords"
and always assign
begin buf bufif0 bufif1
case casex casez cmos
deassign default defparam disable
edge else end endcase endfuction endprimitive endmodule endspecify
endtable endtask event
for force forever fork function
highz0 highz1
if ifnone initial inout input integer
join
large
macromodule medium module
nand negedge nor not notif0 notif1 nmos
or output
parameter pmos posedge primitive pulldown pullup pull0 pull1
rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0
rtranif1
scalared small specify specparam strong0 strong1 supply0
supply1
table task time tran tranif0 tranif1 tri tri0 tri1 triand trior
trireg
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2"Pre-compile Key Words"
`accelerate `autoexpand_vectornets
`celldefine
`default_decay_time `default_nettype `default_trireg_strength
`define `delay_mode_distributed `delay_mode_path `delay_mode_unit
`delay_mode_zero
`else `endcelldefine `endif `endprotect `expand_vectornets
`ifdef `include
`noaccelerate `noexpand_vectornets `noremove_gatenames
`noremove_netnames `nounconnected_drive
`protect `protecte
`remove_gatenames `remove_netnames `reset `resetall
`timescale
`unconnected_drive `undef
/C3"System Fuction"
$async$and$array $async$nand$array $async$or$array $async$nor$array
$async$and$plane $async$nand$plane $async$or$plane
$async$nor$plane
$bitstoreal
$countdrivers
$display $dist_chi_square $dist_erlang $dist_exponential
$dist_normal $dis_poisson $dist_t $dist_uniform $dumpall $dumpfile
$dumplimit $dumpoff $dumpon $dumpvars
$fclose $fdisplay $finish $fmonitor $fopen $fstrobe $fwrite
$getpattern
$hold
$incsave $input $itor
$key
$list $log
$monitor $monitoroff $monitoron
$nokey $nolog
$period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove
$random $readmemb $readmemh $realtime $realtobits $recovery
$reset_count $reset_value $restart $rtoi
$save $scale $scope $setup $setuphold $showscopes $showvars $skew
$sreadmemb $sreadmemh $stime $stop $strobe $sync$and$array
$sync$nand$array $sync$or$array $sync$nor$array $sync$and$plane
$sync$nand$plane $sync$or$plane $sync$nor$plane
$time $timeformat
$width $write
/C4"Operators"
@
*
+
-
=
// /
%
&
>
<
^
!
|

VHDL.uew文件内容如下（文件自己创建即可）：

/L12"VHDL" Line Comment = -- Nocase Block Comment On = -- Block
Comment Off = -- File Extensions = VHD
/Function String = "%entity"
/Delimiters = ~!@$%^&*()+=|\/{}[]:;"<>
,.?/
/C1
abs access after alias all and architecture array assert
attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity signal shared sla sll sra srl subtype
then to transport type
unaffected units until use
variable
wait when while with
xnor xor
/C2
bit bit_vector boolean
integer
real
std_logic std_logic_vector
/C3
=
<
>
:
/C4
'event 'right
/C5
ActivPullUp AndN And2FF AndNFF
Cnt1Bit CntNBit CntNBitDown CntNBitMod CntNBitOe CntNBitSLd
CntNBitSR CntNBitUpDown CompNBit CompNBitFF
DiffH2LWithFF DiffL2HWithFF Dff1 Dff1NegClk Dffn
Encode4to5
Mux1of2 Mux1of8 Mux1Vof2V Mux1Vof3V Mux1Vof4V
PreScale1Bit PreScale1BitAR PreScale1BitARNegClk PreScaleNBit
PreScaleNBitAR
Reg1Bit Reg1BitAR Reg1BitR RegNBit RegNBitAR RSFFAsync RSFFsync
RsSynchronizer
ShiftP2SRegNBitAR ShiftRegNBitAR ShiftS2SRegNBit SRFFsync
SyncAndDiffL2HWithFF SyncAndDiffH2LWithFF SyncAndDiffL2HWithFFAndFg
SyncAndDiffH2LWithFFAndFg SyncAndDiffLL2HHWithFF
SyncAndDiffHH2LLWithFF SyncAndDiffLL2HHWithFFAndFg
SyncAndDiffHH2LLWithFFAndFg
/C6
ActivPullUp_arch AndN_arch And2FF_arch AndNFF_arch
Cnt1Bit_arch CntNBit_arch CntNBitDown_arch CntNBitMod_arch
CntNBitOe_arch CntNBitSLd_arch CntNBitSR_arch CntNBitUpDown_arch
CompNBit_arch CompNBitFF_arch
DiffH2LWithFF_arch DiffL2HWithFF_arch Dff1_arch Dff1NegClk_arch
Dffn_arch
Encode4to5_arch
Mux1of2_arch Mux1of8_arch Mux1Vof2V_arch Mux1Vof3V_arch
Mux1Vof4V_arch
PreScale1Bit_arch PreScale1BitAR_arch PreScale1BitARNegClk_arch
PreScaleNBit_arch PreScaleNBitAR_arch
Reg1Bit_arch Reg1BitAR_arch Reg1BitR_arch RegNBit_arch
RegNBitAR_arch RSFFAsync_arch RSFFsync_arch
RsSynchronizer_arch
ShiftP2SRegNBitAR_arch ShiftRegNBitAR_arch ShiftS2SRegNBit_arch
SRFFsync_arch SyncAndDiffL2HWithFF_arch SyncAndDiffH2LWithFF_arch
SyncAndDiffL2HWithFFAndFg_arch
SyncAndDiffH2LWithFFAndFg_arch SyncAndDiffLL2HHWithFF_arch
SyncAndDiffHH2LLWithFF_arch SyncAndDiffLL2HHWithFFAndFg_arch
SyncAndDiffHH2LLWithFFAndFg_arch

2.
打开UltraEdit15.0，在工具栏中按下面路径打开对话框：高级——配置——编辑器显示——语法高亮

3.
将对话框中“文档的完整目录名称”选项框改变成另外任意文件夹名称，点击应用；然后，再将其换回成“xxx\wordfiles”，点击应用。此时我们添加到文件夹wordfiles中的两个文件就起作用了，Verilog和VHDL语言可以高亮显示。