verilog语法求助

verilog语法求助

你是不是错误提示：Error(10200):VerilogHDLConditionalStatementerrorat……:cannotmatchoperand(s)intheconditiontothecorrespondingedgesintheenclosingeventcontrolofthealwaysconstruct这是因为，你的“always@(posedgeclkornegedger_est)”表明在clk上升沿或r_est下降沿这两个敏感事件发生时always语句块得以触发；而always中的if条件语句必须至少有一个条件指向其中一个敏感事件（边界标识符）；所以写成“if（r_est)else”就会出错。你可以把“always@(posedgeclkornegedger_est)”改为“always@(posedgeclkorposedger_est)”再编译试试，应该就没问题了。你右键该错误点击“Help”里是这么说的：CAUSE:InaconditionalstatementatthespecifiedlocationinaVerilogDesignFile(.v),youspecifiedaconditionthatQuartusIIIntegratedSynthesiscannotusetoclassifytheedgesintheenclosingalwaysconstruct'seventcontrol.Whenaneventcontrolcontainsmultipleedges,QuartusIIIntegratedSynthesisdistinguishestheasynchronouscontrolsignalsfromtheclockbyanalyzingtheconditionalstatementsinthealwaysconstruct.Forexample,thefollowingcodefragmentcontainsanalwaysconstructwhoseeventcontrolcontainsthreeedges---twoasynchronousresetsandaclock.always@(posedgeclkorposedgerst1orposedgerst2)beginif(rst1||rst2)q<=1'b0;elseq<=d;endQuartusIIIntegratedSynthesisusestheifconditiontoidentifythetwoasynchronousresetsand,byimplication,theclock.Foredgeclassification,QuartusIIIntegratedSynthesisrequiresthataconditionfallintooneoftwocategories.Itcanrefertoasingleedgeidentifier(tomatchposedgeevents)oritscomplement(tomatchnegedgeevents),forexample,rst1,!rst1,rst1==1'b1,rst1==1'b0.ItcanalsoORtwoormoreexpressionsthateachrefertoasingleedgeidentifieroritscomplement,forexample,(rst1||rst2),(!rst1||!rst2).Youcanreceivethiserrorifyourconditiontestsforthewrongpolarity,orifittestsforthevalueofavariablethatisnotanedgeintheeventcontrol.Forexample,tomatchaposedgerstevent,theconditionmustberstorrst=1'b1.Finally,youcanreceivethiserrorifyouareattemptingtouseasingleconditionexpressiontotestforbothanasynchronousreset/setandasynchronousreset/setcondition.Thefollowingcodefragmentcontainsanexampleofanillegalconditionexpression:always@(posedgeclkorposedgerst)beginif(rst||sync_rst)q<=1'b0;elseq<=d;endQuartusIIIntegratedSynthesisgeneratesthiserrormessagewhencompilingthisdesignbecauseitcannotmatchsync_rsttoanedgeonthesensitivitylist.其中关键的语句我摘译一下，不一定译得准确，不过大体意思我想你应该可以了解了：原因：……指定了一个条件，QuartusII综合器不能够将该条件用于在封闭的always结构的事件控制中对边界进行区分。当一个事件控制中包含多重边界，QuartusII综合器通过分析always结构中的条件语句来对时钟和异步控制信号加以区分。……QuartusII综合器采用if条件来鉴别两个异步reset信号，并隐含地鉴别了clock信号。为了分类的需要，QuartusII综合器需要有一个条件落入两个类别之一。它可以指向一个单独的边界标识符（以匹配posedge事件）或它的补语（以匹配negedge事件），例如，rst1,!rst1,rst1==1'b1,rst1==1'b0。它也可以是OR两个或的表达式，其中每一个指向一个单独的边界标识符或它的补语……当你的条件测试发现错误极性，或者它测试变量的值，但该值在事件控制中并不是一个边界时，你会接到这个错误。例如，为了匹配一个posedgerst事件，条件必须是rst或rst=1'b1。编译错误时多看看Help，讲得很详细~