verilog fft ip核多通道仿真
答案:1 悬赏:50 手机版
解决时间 2021-03-17 02:11
- 提问者网友：浮克旳回音
- 2021-03-16 17:57
verilog fft ip核多通道仿真
最佳答案
- 五星知识达人网友：佘樂
- 2021-03-16 19:36
always@(posedge clk) begin
i <= i + 1;
if(start) begin
case(i)
3'b000: xn0_re <= 8'd20;
3'b001: xn0_re <= 8'd30;
3'b010: xn0_re <= 8'd40;
3'b011: xn0_re <= 8'd50;
3'b100: xn0_re <= 8'd60;
3'b101: xn0_re <= 8'd70;
3'b110: xn0_re <= 8'd80;
3'b111: xn0_re <= 8'd000;
default;
endcase
end
end
always@(posedge clk) begin
j <= j + 1;
if(start) begin
case(j)
3'b000: xn1_re <= 8'd30;
3'b001: xn1_re <= 8'd40;
3'b010: xn1_re <= 8'd50;
3'b011: xn1_re <= 8'd60;
3'b100: xn1_re <= 8'd70;
3'b101: xn1_re <= 8'd80;
3'b110: xn1_re <= 8'd90;
3'b111: xn1_re <= 8'd000;
default;
endcase
end
end
这样试试追问你说的方法我也试过，效果和我的一样，也只有xn1_re输入
i <= i + 1;
if(start) begin
case(i)
3'b000: xn0_re <= 8'd20;
3'b001: xn0_re <= 8'd30;
3'b010: xn0_re <= 8'd40;
3'b011: xn0_re <= 8'd50;
3'b100: xn0_re <= 8'd60;
3'b101: xn0_re <= 8'd70;
3'b110: xn0_re <= 8'd80;
3'b111: xn0_re <= 8'd000;
default;
endcase
end
end
always@(posedge clk) begin
j <= j + 1;
if(start) begin
case(j)
3'b000: xn1_re <= 8'd30;
3'b001: xn1_re <= 8'd40;
3'b010: xn1_re <= 8'd50;
3'b011: xn1_re <= 8'd60;
3'b100: xn1_re <= 8'd70;
3'b101: xn1_re <= 8'd80;
3'b110: xn1_re <= 8'd90;
3'b111: xn1_re <= 8'd000;
default;
endcase
end
end
这样试试追问你说的方法我也试过，效果和我的一样，也只有xn1_re输入
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