FPGA Verilog代码编写问题

FPGA Verilog代码编写问题

always @(posedge keydone, posedge reset) begin
  if (reset)
      {SH,SL,FH,FL} <= 0;
      count <= 0;
  else
      {SH,SL,FH,FL} <= {SL,FH,FL,data_in};
      if (count == 5)
          count <= 1;
      else
          count <= count + 1;
end

assign data_ready = count == 4;