verilog hdl 怎么转换成vhdl

程序：
always @ (posedge clk_in or negedge reset)
begin
if(!reset)
begin
cnt_clk_in <= 0;
state_w <= stept0;
{w1,w2} <=2'bol;
end
else
begin
cnt_clk_in <= cnt_clk_in + l;
cnt_ww <= cnt_ww + 1;
case(state_w)
stept0:
begin
state_w <= steptl;
w1 <= 1;
w2 <= 0;
end
stept1:
begin
case(cnt_clk_in)
s2:
begin
w1 <= 0;
w2 <= l;
end
150:
begin
state_w <= stept2;
cnt_clk_in <= 0;
w1 <= 1;
w2 <= 0;
end
endcase
end
stept2:
begin
if(cnt_ww == s3)
begin
cnt_ww <= 0;
state_w <= stept0;
cnt_clk_in <= 0;
end
else
if(cnt_elk_in == s2)
begin
cnt_clk_in <= 0;
w1 <=~w1;
w2 <=~w2;
end
end
endcase
end
end

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