vhdl 编写的4-16译码器？

代码

library ieee;
use ieee.std_logic_1164.all;
entity decoder4_16 is
port(data:in std_logic_vector(3 downto 0);
en :in std_logic;
y:out std_logic_vector(15 downto 0));
end entity decoder4_16;
architecture arch1 of decoder4_16 is
begin
process(en,data)
begin
if en='1' then
case data is
when "0000"=> y(15 downto 0)<="1111111111111110";
when "0001"=> y(15 downto 0)<="1111111111111101";
when "0010"=> y(15 downto 0)<="1111111111111011";
when "0011"=> y(15 downto 0)<="1111111111110111";
when "0100"=> y(15 downto 0)<="1111111111101111";
when "0101"=> y(15 downto 0)<="1111111111011111";
when "0110"=> y(15 downto 0)<="1111111110111111";
when "0111"=> y(15 downto 0)<="1111111101111111";
when "1000"=> y(15 downto 0)<="1111111011111111";
when "1001"=> y(15 downto 0)<="1111110111111111";
when "1010"=> y(15 downto 0)<="1111101111111111";
when "1011"=> y(15 downto 0)<="1111011111111111";
when "1100"=> y(15 downto 0)<="1110111111111111";
when "1101"=> y(15 downto 0)<="1101111111111111";
when "1110"=> y(15 downto 0)<="1011111111111111";
when "1111"=> y(15 downto 0)<="0111111111111111";
when others =>y(15 downto 0)<="1111111111111111";
end case;
end if;
end process;
end architecture;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity trans38 is port( A:in std_logic_vector(2 downto 0); EN:in std_logic; Y:out std_logic_vector(7 downto 0) ); end trans38; architecture dec_behave of trans38 is signal sel:std_logic_vector(3 downto 0); begin sel<=A&EN; with sel select Y<= "00000001" when "0001", "00000010" when "0011", "00000100" when "0101", "00001000" when "0