VHDL中 仿真时候出错：logic level does not match!!

library ieee;--this is a Dflip-flop
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff1 is
port(d1:in std_logic;
clk:in std_logic;
clr:in std_logic;
q1:out std_logic);
end dff1;
architecture ar1 of dff1 is
begin
process(clk,clr,d1)
begin
if clr='1' then
q1<='0';
elsif clk'event and clk='1' then
q1<=d1;
end if;
end process;
end architecture ar1;

library ieee;--this is a MultipleChooser
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mulch is
port(d2:in std_logic;
tc:in std_logic;
sd:in std_logic;
q2:out std_logic);
end mulch;
architecture ar2 of mulch is
begin
q2<=(d2 and tc)or(not(tc) and (sd));
end architecture ar2;

library ieee;--this is a Scanflip-flop
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity scanff is
port(d:in std_logic;
tc:in std_logic;
sd:in std_logic;
clk:in std_logic;
clr:in std_logic;
q:out std_logic);
end scanff;
architecture ar3 of scanff is
component dff1 is
port(d1:in std_logic;
clk:in std_logic;
clr:in std_logic;
q1:out std_logic);
end component dff1;
component mulch is
port(d2:in std_logic;
tc:in std_logic;
sd:in std_logic;
q2:out std_logic);
end component mulch;
signal si1:std_logic;
begin
c1:mulch port map(d2=>d,tc=>tc,sd=>sd,q2=>si1);
c2:dff1 port map(d1=>si1,clk=>clk,clr=>clr,q1=>q);
end architecture ar3;

生成网表之后仿真，出错如下：
Error: Logic level [0] does not match expected logic level [0] for node "q" at time 0 ps
q的Scan触发器的输出，求高手解答。

我按照一楼说的定义一个信号signal qq:std_logic;
然后将句出错的例化语句改成c2:dff1 port map(d1=>si1,clk=>clk,clr=>clr,q1=>qq);
最后再加句，q<=qq；
还是不行 错误仍然是：
Error: Logic level [0] does not match expected logic level [0] for node "q" at time 0 ps
谢谢一楼的回答，不过还是请高手帮解决。

你试着定义一个信号signal qq:std_logic;
然后将句出错的例化语句改成c2:dff1 port map(d1=>si1,clk=>clk,clr=>clr,q1=>qq);
最后再加句，q<=qq；

你好！ CASE JNK IS WHEN "00" => NULL; WHEN "01" => Q<='0';--你定义的Q是std_logic类型，但你赋值的时候由于没加单引号，被认为是integer类型了，所以应加单引号，下一句也是 WHEN "10" => Q<='1'; 另外Q好像应该定义为buffer模式才行吧。 如果对你有帮助，望采纳。