懂ABLE语言和VHDL语言的进来!!

能帮我把这三个ABLE程序换成VHDL程序吗?
MODULE ct7
cin ,r pin ;
o0 ,o1 ,o2 ,o3 ,o4 ,o5 ,o6 ,o7 pin istype ’reg’;
count = [o7 ,o6 ,o5 ,o4 ,o3 ,o2 ,o1 ,o0 ] ;
equations
count . clk = cin ;
count . aclr = ! r ;
count = count + 1 ;
END

MODULE LJ
t0 , t1 , t2 , t3 , t4 , t5 , t6 , t7 pin ;
d0 , d1 , d2 , d3 , d4 , d5 , d6 , d7 pin ;
az ,af pin ;
cin ,fcin pin ;
n0 ,n1 ,n2 ,n3 ,n4 ,n5 ,n6 ,n7 ,out node ;
equations
n0 = t0 &d7 ;
n1 = t1 & ! t0 &d6 ;
n2 = t2 & ! t1 & ! t0 &d5 ;
n3 = t3 & ! t2 & ! t1 & ! t0 &d4 ;
n4 = t4 & ! t3 & ! t2 & ! t1 & ! t0 &d3 ;
n5 = t5 & ! t4 & ! t3 & ! t2 & ! t1 & ! t0 &d2 ;
n6 = t6 & ! t5 & ! t4 & ! t3 & ! t2 & ! t1 & !
t0 &d1 ;
n7 = t7 & ! t6 & ! t5 & ! t4 & ! t3 & ! t2 & !
t1 & ! t0 &d0 ;
out = n0 # n1 # n2 # n3 # n4 # n5 # n6 # n7 ;
az = ! cin &out ;
af = ! fcin &out ;
END

MODULE DS
clk ,fw ,r pin ;
cf pin ;
o0 ,o1 ,o2 ,o3 ,o4 node istype ’reg’;
count = [o4 ,o3 ,o2 ,o1 ,o0 ] ;
equations
count . clk = clk & ! (o4 &o3 &o2 &o1 &o0) ;
count . aclr = fw ;
cf = ! (o4 &o3 &o2 &o1 &o0) & ! fw &clk &r ;
count = count + 1 ;
END

第一个：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT(clk: IN std_logic;
aclk：IN std_logic;
count：OUT std_logic_vector(7 downto 0));
END counter；
ARCHITECTURE ct7 OF counter IS
SIGNAL n:std_logic_vector(7 downto 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL (clk'event and clk='1')；
IF aclk='0' THEN
n<= (OTHERS =>'0');
ELSE
n<= n+1;
END IF;
END PROCESS;
count<=n;
END ct7

第二个：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY LJ IS
P ORT(
t0,t1,t2,t3,t4,t5,t6,t7 in std_logic;
d0,d1,d2,d3,d4,d5,d6,d7 in std_logic;
az,af out std_logic;
cin,fcin in std_logic;
)
END LJ
ARCHITECTURE eval OF LJ IS
SIGNAL n0,n1,n2,n3,n4,n5,n6,n7 :std_logic;
BEGIN
n0 <= t0 AND d7;
n1 <= t1 AND NOT t0 AND d6;
n2 <= t2 AND NOT t1 AND NOT t0 AND d5 ;
n3 <= t3 AND NOT t2 AND NOT t1 AND NOT t0 AND d4 ;
n4 <= t4 AND NOT t3 AND NOT t2 AND NOT t1 AND NOT t0 AND d3 ;
n5 <= t5 AND NOT t4 AND NOT t3 AND NOT t2 AND NOT t1 AND NOT t0 AND d2;
n6 <= t6 AND NOT t5 AND NOT t4 AND NOT t3 AND NOT t2 AND NOT t1 AND NOT t0 AND d1 ;
n7 <= t7 AND NOT t6 AND NOT t5 AND NOT t4 AND NOT t3 AND NOT t2 AND NOT t1 AND NOT t0 AND d0 ;
out <= n0 OR n1 OR n2 OR n3 OR n4 OR n5 OR n6 OR n7;
az <= NOT cin AND out ;
af <= NOT fcin AND out ;
END eval;

第三个：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT(clk,fw,r,pin: IN std_logic;
cf: OUT std_logic
count：OUT std_logic_vector(4 downto 0));
END counter；
ARCHITECTURE ds OF counter IS
SIGNAL n:std_logic_vector(4 downto 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL (clk'event and clk='1')；
IF fw='0' THEN
n<= (OTHERS =>'0');
ELSE
n<= n+1;
END IF;
END PROCESS;
cf<=NOT (n(4) AND n(3) AND n(2) AND n(1) AND m(0)) AND NOT fw AND clk NOT r ;
count<=n;
END ds

看在这么多代码，回答的人又少，能不能多给点分啊？

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