eda编程9人表决器
答案:1 悬赏:40 手机版
解决时间 2021-11-11 13:07
- 提问者网友:做自己de王妃
- 2021-11-11 08:16
eda编程9人表决器
最佳答案
- 五星知识达人网友:一秋
- 2021-11-11 08:47
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity selector is
port(a:in std_logic_vector(8 downto 0);
r,g:out std_logic;
ledout:out std_logic_vector(6 downto 0));
end selector;
architecture rtl of selector is
signal led:std_logic_vector(6 downto 0);
signal count:std_logic_vector(3 downto 0);
begin
process(a)
variable cnt:std_logic_vector(3 downto 0);
begin
cnt:="0000";
for i in 0 to 8 loop
if a(i)='1' then
cnt:=cnt+'1';
end if;
end loop;
if(cnt>="0101" and cnt<="1001") then
g<='1';
r<='0';
elsif(cnt>="0000" and cnt<="0100") then
g<='0';
r<='1';
end if;
count<=cnt;
end process;
ledout<=not led;
with count select
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"when others;
end rtl;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity selector is
port(a:in std_logic_vector(8 downto 0);
r,g:out std_logic;
ledout:out std_logic_vector(6 downto 0));
end selector;
architecture rtl of selector is
signal led:std_logic_vector(6 downto 0);
signal count:std_logic_vector(3 downto 0);
begin
process(a)
variable cnt:std_logic_vector(3 downto 0);
begin
cnt:="0000";
for i in 0 to 8 loop
if a(i)='1' then
cnt:=cnt+'1';
end if;
end loop;
if(cnt>="0101" and cnt<="1001") then
g<='1';
r<='0';
elsif(cnt>="0000" and cnt<="0100") then
g<='0';
r<='1';
end if;
count<=cnt;
end process;
ledout<=not led;
with count select
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"when others;
end rtl;
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