高分求 基于VHDL语言设计的数字时钟

高分求 基于VHDL语言设计的数字时钟

-------------------程序（.vhd文件）如下---------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock is
port(
clk : in std_logic;
rst : in std_logic;
inc_min : in std_logic;
sub_min : in std_logic;
inc_hour : in std_logic;
sub_hour : in std_logic;
sel : out std_logic_vector(3 downto 0);
q : out std_logic_vector(7 downto 0));
end clock;

architecture Behavioral of clock is
signal sec_counter1:std_logic_vector(3 downto 0);
signal sec_counter2:std_logic_vector(3 downto 0);
signal min_counter1:std_logic_vector(3 downto 0);
signal min_counter2:std_logic_vector(3 downto 0);
signal hour_counter1:std_logic_vector(3 downto 0);
signal hour_counter2:std_logic_vector(3 downto 0);
signal divcounter : std_logic_vector(27 downto 0);
signal div_clk : std_logic;
signal scancounter : std_logic_vector(10 downto 0);
signal scan_clk : std_logic;
signal scan_out : std_logic_vector(2 downto 0);
signal secseg1,secseg2,minseg1,minseg2,hourseg1,hourseg2:std_logic_vector(7downto 0);
begin

--计数时钟，对外部输入时钟分频，此处只适用于仿真，实际进行时间计数时，分频后时钟应该满足1HZ。

process(rst,clk)
begin
if(rst='0')then
divcounter <= (others=>'0');
div_clk<='0';
elsif(rising_edge(clk)) then
if(divcounter=X"17D7840") then
divcounter <= (others=>'0');
div_clk<=not div_clk;
else
divcounter<=divcounter+'1';
end if;
end if;
end process;

--仿真时数码管扫描??钟，实??中?韪菥咛迩榭鼋械鹘馐敝悠德?process(rst,clk)
begin
if(rst='0')then
scancounter<=(others=>'0');
scan_clk<='0';
elsif(rising_edge(clk)) then
if(scancounter="00011111111") then
scancounter<=(others=>'0');
scan_clk<=not scan_clk;
else
scancounter<=scancounter+'1';
end if;
end if;
end process;

--时钟计数部分主进程
--时钟复位
clock:process(div_clk,rst)
begin
if(rst='0')then
sec_counter1<=X"0";
sec_counter2<=X"0";
min_counter1<=X"0";
min_counter2<=X"0";
hour_counter1<=X"0";
hour_counter2<=X"0";

--手动调分，递增
elsif(rising_edge(div_clk))then
if(inc_min='0') then
if(min_counter1=X"9") then
min_counter1<=X"0";
if(min_counter2>=X"5") then
min_counter2<=X"0";
else
min_counter2<=min_counter2+1;
end if;
else
min_counter1<=min_counter1+1;
end if;

--手动调分，递减
elsif(sub_min='0') then
if(min_counter1=X"0") then
min_counter1<=X"9";
if(min_counter2=X"0")then
min_counter2<=X"5";
else
min_counter2<=min_counter2-1;
end if;
else
min_counter1<=min_counter1-1;
end if;
--手动调时，增时
elsif(inc_hour='0') then
if(hour_counter2=X"2")then
if(hour_counter1=X"3")then
hour_counter1<=X"0";
hour_counter2<=X"0";
else
hour_counter1<=hour_counter1+1;
end if;
else
if(hour_counter1=X"9") then
hour_counter1<=X"0";
hour_counter2<=hour_counter2+1;
else
hour_counter1<=hour_counter1+1;
end if;
end if;
--手动调时，减时
elsif(sub_hour='0') then
if(hour_counter1=X"0")then
if(hour_counter2=X"0")then
hour_counter1<=X"3"; hour_counter2<=X"2";
else
hour_counter2<=hour_counter2-1;
hour_counter1<=X"9";
end if;
else
hour_counter1<=hour_counter1-1;
end if;
--时分秒正常计数
else
if(sec_counter1>=X"9") then
sec_counter1<=X"0";
if(sec_counter2>=X"5") then
sec_counter2<=X"0";
if(min_counter1>=X"9") then
min_counter1<=X"0";
if(min_counter2>=X"5") then
min_counter2<=X"0";
if(hour_counter2=X"2") then
if(hour_counter1=X"3") then
hour_counter1<=X"0";
hour_counter2<=X"0";
else
hour_counter1<=hour_counter1+1;
end if;
else
if(hour_counter1=X"9") then
hour_counter1<=X"0";
hour_counter2<=hour_counter2+1;
else
hour_counter1<=hour_counter1+1;
end if;
end if;
else
min_counter2<=min_counter2+1;
end if;
else
min_counter1<=min_counter1+1;
end if;
else
sec_counter2<=sec_counter2+1;
end if;
else
sec_counter1<=sec_counter1+1;
end if;
end if;
end if;

end process clock;
--生成扫描时钟
process(rst,scan_clk)
begin
if (rst='0') then
scan_out<="000";
elsif(rising_edge(scan_clk)) then
if(scan_out="011")then
scan_out<="000";
else
scan_out<=scan_out+1;
end if;
end if;
end process;
--扫描输出进程
process(scan_out)
begin
case scan_out is
when "000" => q<=secseg1; sel<="0001";
when "001" => q<=secseg2; sel<="0010";
when "010" => q<=minseg1; sel<="0100";
when "011" => q<=minseg2; sel<="1000";
--when "100" => q<=hourseg1; --sel<="100";
--when "101" => q<=hourseg2; --sel<="101";
when others => q<="00000000";sel<="0000";
end case;
end process;
--秒低位显示
second_counter1:process(sec_counter1)
begin
case sec_counter1 is
when "0000" => secseg1<="10111111";
when "0001" => secseg1<="10000110";
when "0010" => secseg1<="11011011";
when "0011" => secseg1<="11001111";
when "0100" => secseg1<="11100110";
when "0101" => secseg1<="11101101";
when "0110" => secseg1<="11111101";
when "0111" => secseg1<="10000111";
when "1000" => secseg1<="11111111";
when "1001" => secseg1<="11101111";
when others => secseg1<="11111111";
end case;
end process second_counter1;
--秒高位显示
second_counter2:process(sec_counter2)
begin
case sec_counter2 is
when "0000" => secseg2<="00111111";
when "0001" => secseg2<="00000110";
when "0010" => secseg2<="01011011";
when "0011" => secseg2<="01001111";
when "0100" => secseg2<="01100110";
when "0101" => secseg2<="01101101";
when others => secseg2<="01111111";
end case;
end process second_counter2;
--分低位显示
minute_counter1:process(min_counter1)
begin
case min_counter1 is
when "0000" => minseg1<="10111111";
when "0001" => minseg1<="10000110";
when "0010" => minseg1<="11011011";
when "0011" => minseg1<="11001111";
when "0100" => minseg1<="11100110";
when "0101" => minseg1<="11101101";
when "0110" => minseg1<="11111101";
when "0111" => minseg1<="10000111";
when "1000" => minseg1<="11111111";
when "1001" => minseg1<="11101111";
when others => minseg1<="11111111";
end case;
end process minute_counter1;
--分高位显示
minute_counter2:process(min_counter2)
begin
case min_counter2 is
when "0000" => minseg2<="00111111";
when "0001" => minseg2<="00000110";
when "0010" => minseg2<="01011011";
when "0011" => minseg2<="01001111";
when "0100" => minseg2<="01100110";
when "0101" => minseg2<="01101101";
when others => minseg2<="01111111";
end case;
end process minute_counter2;
--小时低位显示
hor_counter1:process(hour_counter1)
begin
case hour_counter1 is
when "0000" => hourseg1<="10111111";
when "0001" => hourseg1<="10000110";
when "0010" => hourseg1<="11011011";
when "0011" => hourseg1<="11001111";
when "0100" => hourseg1<="11100110";
when "0101" => hourseg1<="11101101";
when "0110" => hourseg1<="11111101";
when "0111" => hourseg1<="10000111";
when "1000" => hourseg1<="11111111";
when "1001" => hourseg1<="11101111";
when others => hourseg1<="11111111";
end case;
end process;
--小时高位显示

hor_counter2:process(hour_counter2)
begin
case hour_counter2 is
when "0000" => hourseg2<="00111111";
when "0001" => hourseg2<="00000110";
when "0010" => hourseg2<="01011011";
when others => hourseg2<="01111111";
end case;
end process;
end Behavioral;
------------------引脚（.ucf文件）如下-------------------
# clk : in std_logic;
# rst : in std_logic;
# inc_min : in std_logic;
# sub_min : in std_logic;
# inc_hour : in std_logic;
# sub_hour : in std_logic;
# sel : out std_logic_vector(2 downto 0);
# q : out std_logic_vector(7 downto 0));

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p80" ;
NET "inc_hour" LOC = "p20" | PULLUP ; #SW3
NET "inc_min" LOC = "p32" ; #SW1
NET "q<0>" LOC = "p47" ; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = JD4 (a)
NET "q<1>" LOC = "p50" ; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = JD5 (b)
NET "q<2>" LOC = "p48" ; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = JD6(c)
NET "q<3>" LOC = "p41" ; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = JD7(d)
NET "q<4>" LOC = "p45" ; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = JD8(e)
NET "q<5>" LOC = "p42" ; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = JD3(f)
NET "q<6>" LOC = "p49" ; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = JD1(g)

NET "q<7>" LOC = "p40" ;
NET "rst" LOC = "p43" ; #SW0

NET "sel<0>" LOC = "p34" ; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = SEG_SELIN1
NET "sel<1>" LOC = "p35" ; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = SEG_SELIN2
NET "sel<2>" LOC = "p36" ; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = SEG_SELIN3
NET "sel<3>" LOC = "p39" ; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = SEG_SELIN4

NET "sub_hour" LOC = "p14" | PULLUP ; #SW4

NET "sub_min" LOC = "p26" ; #SW2

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE