Error (10170): Verilog HDL syntax error at bijiaoqi.v(1) near text ";"; expecting ".&

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bijiaoqi is
port(a,b:instd_logic_vector(2 downto 0);
sel_f:instd_logic_vector(1 downto 0);
q:outBoolean);
end;
architecture one of bijiaoqi is
begin
process(sel_f,a,b)
begin
case sel_f is
when”00” => q <= a=b;
when”01” => q <= awhen”10” => q <= a>b;
when others => q <=false;
end case;
end process;
end one;

你具体要实现什么功能，感觉你有些地方语法就不对。